A Polynomial Time Optimal Algorithm for Simultaneous Bu er and Wire Sizing

An interconnect joining a source and a sink is divided into xed length uniform width wire segments and some adjacent segments have bu ers in between The problem we considered is to simultaneously size the bu ers and the segments so that the Elmore delay from the source to the sink is minimized Previously no polynomial time al gorithm for the problem has been reported in literature In this paper we present a polynomial time algorithm SBWS for the simultaneous bu er and wire sizing prob lem SBWS is an iterative algorithm with guaranteed convergence to the optimal solution It runs in quadratic time and uses constant memory for computation Also experimental results show that SBWS is extremely ef cient in practice For example for an interconnect of segments and bu ers the CPU time is only second Introduction In the past gate delay was the dominating factor in circuit design However as the feature size of VLSI de vices continues to decrease interconnect delay becomes increasingly important Nowadays feature size has been down to m in advance technology Interconnect delay has become the dominating factor in determining system performance In many systems designed today as much as to of clock cycle are consumed by interconnect delay It is predicted in that the fea ture size will be reduced to m by and m by So we expect the signi cance of interconnect delay will further increase in the near future Both bu er sizing and wire sizing have been shown to be e ective techniques to reduce interconnect delay and many works have been done during the past few years For example are various results on wire sizing alone applies the sequential quadratic programming approach to simultaneous gate and wire sizing This algorithm is comparatively slow as it has to solve a sequence of quadratic programming subproblems This work was partially supported by the Texas Advanced Re search Program under Grant No and by a grant from the Intel Corporation Also no bound on the run time of the algorithm is re ported gives an algorithm for simultaneous bu er insertion bu er sizing and wire sizing based on dynamic programming However their algorithm runs in pseudo polynomial time and requires a substantial amount of memory give greedy algorithms for simultane ous transistor bu er and wire sizing These algorithms are shown to be very e cient in practice However no bounds on the run time of them are known con siders bu er insertion bu er sizing and wire sizing si multaneously and a closed form optimal solution is ob tained However in that paper only wire area capac itance is considered Wire fringing capacitance which will become more and more signi cant as feature size de creases is ignored Taking wire fringing capacitance into account signi cantly complicates the problem and can only give an approximate solution shows that the si multaneous bu er insertion and wire sizing problem can be formulated as a convex quadratic program The con vex quadratic program has a small size and some special structures and so can be solved very e ciently How ever if bu er sizing is considered also only a brute force enumeration of the bu er sizes is proposed See for a comprehensive survey on previous works In this paper we consider the problem of minimizing interconnect delay by simultaneously sizing bu ers and wire segments Basically an interconnect joining a source and a sink is divided into some xed length uniform width wire segments Some of the adjacent segments have bu ers in between The problem is to determine the bu er sizes and segment widths so that the Elmore delay from the source to the sink is minimized In particular both wire area capacitance and wire fringing capacitance are taken into account and an approach completely dif ferent from that in is required here The details of the problem formulation are discussed in Section We make the following contributions in this paper We present an iterative algorithm SBWS for the simultaneous bu er and wire sizing problem We prove that SBWS always converges to the optimal solution We prove that for an interconnect wire consisting of n bu ers and segments SBWS runs in O n n log time where speci es the precision of com putation see Theorem Since log is bounded by the number of bits in the input the total run time is quadratic to the input size This is the rst polyno mial time algorithm for the simultaneous bu er and wire sizing problem considered in this paper SBWS requires only constant memory for computa tion We demonstrate experimentally that SBWS is also extremely e cient in practice For example for an interconnect of segments and bu ers the CPU time is only second Besides we observe that SBWS runs in linear time in practice The rest of the paper is organized as follows In Sec tion we present the formulation of the simultaneous bu er and wire sizing problem In Section the al gorithm SBWS its optimality proof and its run time analysis are presented In Section some experimental results to show the e ciency of SBWS are presented In Section we discuss some extensions of our results Problem Formulation In this paper a component means either a bu er or a wire segment Given a source with driver resistance RD a sink with load capacitance CL the source and the sink are linked by an interconnect consisting of n components The i th component is either a bu er of size xi or a wire segment of width xi The simultaneous bu er and wire sizing problem is to minimize the delay from the source to the sink with respect to x xn See Figure for an illustration